1. Technical Field
Various embodiments of the present disclosure relate to power semiconductor devices and, more particularly, to lateral power integrated devices having a low on-resistance value.
2. Related Art
Integrated devices having functions of both a controller and a driver are often referred to as smart power devices. In general, output circuits of the smart power devices may be designed to include power integrated devices such as lateral double diffused MOS (LDMOS) transistors operating at a high voltage. In the power integrated devices, breakdown voltages of the LDMOS transistors, for example, a drain junction breakdown voltage and a gate dielectric breakdown voltage are important factors that directly influence the stable operation of the LDMOS transistors. In addition, an on-resistance (Ron) value of the LDMOS transistors is also an important factor that influences electrical characteristics of the LDMOS transistors, for example, a current drivability of the LDMOS transistors.
To improve the drain junction breakdown voltage of the LDMOS transistors, a doping concentration of a drift region between a drain region and a channel region has to be reduced or a drift length of carriers in the drift region corresponding to a length of a current path in the drift region has to be increased. However, in such a case, the on-resistance (Ron) of the LDMOS transistors may increase, degrading the current drivability of the LDMOS transistors. When the doping concentration of the drift region between the drain region and the channel region increases or the drift length in the drift region decreases, the on-resistance (Ron) of the LDMOS transistors may be reduced, thereby improving the current drivability of the LDMOS transistors, however the drain junction breakdown voltages of the LDMOS transistors may be lowered. That is, in the LDMOS transistors, the on-resistance and the drain junction breakdown voltage may have a trade-off relationship.